我的征尘是星辰大海。。。

The dirt and dust from my pilgrimage forms oceans of stars...

-------当记忆的篇章变得零碎，当追忆的图片变得模糊，我们只能求助于数字存储的永恒的回忆

作者:黄教授

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AI时代的总线战争

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原始脚本

AI 时代的总线战争，协议主导权之争下的国产突围。
当所有人还在紧盯英伟达 H200的算力、ASML 光刻机的精度时，AI 大模型训练的核心战场早已悄然转移。
单卡性能的提升已逼近物理与成本极限，卡间数据传输的带宽与时延才是当前制约算力突破的真正瓶颈。
如今的 AI 训练早已不是单卡独秀，而是万卡协同。
数据在算力卡之间的流转效率直接决定了大模型训练的速度与成本。
遗憾的是，这一关键痛点不仅被普通人忽视，就连不少行业从业者仍执着于单卡性能的比拼，却未察觉真正的算力革命早已发生在卡与卡之间的总线赛道上。
当 AI 大模型对卡间传输的需求以数月翻倍的速度狂飙，传统 PCIe 协议数年一代速率翻倍的迭代节奏早已捉襟见肘。
这场算力需求与传输技术的供需失衡直接引爆了全球 AI 行业的总线战争，谁能主导卡间互联的协议标准，谁就能掌握算力集群的生态话语权。
而这正是决定未来 AI 产业格局的核心战场。
英伟达对高端显卡的出口限制，本质上也是对高带宽互联技术的封锁。
这更印证了总线技术的战略重要性，单卡再强，若无法高效协同，也只是孤立的算力孤岛。
唯有打通卡间传输的高速公路，才能让万卡集群真正释放出颠覆式的算力。
一，为何总线战争是 AI 时代的必争之地？总线作为算力卡间数据流通的高速公路，其带宽、时延与兼容性直接决定了 AI 训练的效率上限。
在大模型参数规模突破万亿，算力集群规模达数千张卡的今天，总线的重要性被推向极致。
性能瓶颈的核心突破口，AI 训练中，卡间数据交换耗时占比已超计算本身。
传统 PCIE 5.0的传输速率远不能满足需求，而定制化互联协议能将时延压制微秒级，带宽提升数倍。
成为突破算力天花板的关键。
生态霸权的前置战场，协议主导权意味着适配规则的制定权。
一旦某类协议形成规模效应，下游硬件厂商、软件开发者、数据中心都将被迫兼容，最终形成赢者通吃的生态壁垒。
自主可控的底层根基，总线控制器协议专利长期被欧美垄断。
若无法掌握自主协议，即便国产算力卡性能达标，也会因传输通道受制于人，陷入卡脖子困境。
二、当前总线战争的格局，四分天下。
生态歌剧面对 PCIE 的滞后性，全球科技巨头纷纷推出定制化互联协议，形成四大阵营歌剧的态势，各有核心优势与生态壁垒。
英伟达 NVLink 行业标杆级存在，凭借 H100、H200的市场垄断地位，实现卡间双向带宽超900GB 每秒，且与 CUDA 生态深度绑定。
其优势在于硬件件加软件加协议的闭环。
缺点是封闭性极强，仅支持英伟达自家显卡，形成技术壁垒。
AMD Infinity Fabric 原 ULA Link ，主打异构兼容，可连接 CPU、GPU、FPGA 等多类设备，带宽与 NVLink 接近，且开 开放程度更高，试图依托服务器市场份额打破英伟达垄断。
但生态成熟度仍有差距。
谷歌 TPU interconnect 为自家 TPU 集群量身定制，聚焦云端大规模训练，具备超低时延的优势。
与 Google Cloud 的生态深度融合，但其应用场景高度集中，通用性不足。
华为 Matrix Link 国产阵营的核心力量，带宽达800GB 每秒以上，支持昇腾系列芯片的全互联。
且兼容 PCIe 协议，兼顾自主化与兼容性，是国内唯一能与国际巨头抗衡的协议方案，但生态覆盖范围仍需拓展。
此外，PCIe 联盟虽在推进6.0速率256GB每秒，7.0速率512GB每秒标准。
但按传统节奏，7.0全面商用需等到2030年前后，完全无法匹配 AI 算力的增长速度，已沦为备用选项。
三、国产阵营的现状，追赶加速，但痛点凸显在国内算力自主化政策推动下，国产总线协议已实现从0到1的突破。
但仍处于追赶者地位，面临三大核心痛点，生态规模不足。
华为 Matrix Link 虽技术达标，但昇腾芯片的市场占有率仍低于英伟达，导致适配的软件框架、第三方硬件数量有限，形成技术可行，但生态不旺的困境。
专利与测试壁垒，欧美企业早于数十年布局总线专利，国产协议面临潜在侵权风险。
同时，协议测试设备认证体系被国外厂商垄断，制约了技术迭代与商业化落地。
协同性不足，国内除华为外，摩尔线程、毕任等企业也在探索自有协议，缺乏统一的行业标准，导致资源分散。
难以形成合力对抗国际巨头。
但值得关注的是，国产阵营已呈现加速追赶态势，MatrixLink 已在政务、金融等国产化项目中规模化应用，曙光等厂商的算力机柜也已适配该协议，部分高校与科研机构开始共建协议测试平台，打破国外认证垄断。
四、国产突围的三大方向与未来趋势。
面对全球竞争，国产总线协议要实现突围，需聚焦技术迭代、加生态共建、加标准统一三大方向，同时顺应行业发展趋势。
一、核心突围路径一，技术上兼容加超越。
坚持自主化为主，兼容性为辅。
在提升协议带宽、降低时延的同时，保持对 PCIE 的兼容，降低数据中心迁移成本，快速扩大应用场景。
二、生态上开放加共建，联合国内硬件厂商、软件开发方、云服务商成立联盟。
开放协议接口，鼓励第三方适配，形成芯片协议软件应用的国产闭环，避免单打独斗。
三、标准上自主加参与，加快制定国产总线协议的行业标准，同时积极参与国际标准制定，争夺话语权，减少专利侵权风险。
二、未来发展趋势，协议专用化加融合化并行。
一方面，针对 AI 训练、边缘计算等场景的专用协议将持续迭代。
另一方面，兼容多场景的通用化协议将成为竞争焦点，兼顾效率与灵活性。
总线加光互联成为标配，为突破铜缆传输距离限制，光纤与定制化总线的结合将成为主流。
实现跨机柜、跨数据中心的高效互联，打破单机柜集群的规模上限。
国产协议规模化应用加国际化拓展，依托国内庞大的算力基建需求，国产协议将先实现规模化落地，再通过一带一路等合作契机，向海外拓展生态，打破欧美垄断。
总结，总线战争，关乎未来10年 AI 话语权。
这场总线战争，本质上是算力传输规则的争夺战，更是全球 AI 产业话语权的重新分配。
传统 PCIe 的滞后为后发者提供了弯道超车的机会，而国产阵营已站在关键的突围节点。
当前，国内虽面临生态、专利、标准等多重挑战，但凭借政策支持、庞大市场需求与技术突破，华为 Matrix Link 等方案已具备突围潜力。
未来，只有将技术自主与生态开放相结合，打破企业间的壁垒，形成国产协议的合力，才能在这场没有硝烟的战争中占据一席之地，为国产 AI 产业构建真正自主可控的底层传输根基。
而对于所有关注 AI 发展的人来说，是时候把目光从单卡性能上移开，卡间的总线赛道才是决定未来算力格局的终极战场。

修正脚本

AI 时代的总线战争，协议主导权之争下的国产突围。
当所有人还在紧盯英伟达 H200的算力、ASML 光刻机的精度时，AI 大模型训练的核心战场早已悄然转移。
单卡性能的提升已逼近物理与成本极限，卡间数据传输的带宽与时延才是当前制约算力突破的真正瓶颈。
如今的 AI 训练早已不是单卡独秀，而是万卡协同。
数据在算力卡之间的流转效率直接决定了大模型训练的速度与成本。
遗憾的是，这一关键痛点不仅被普通人忽视，就连不少行业从业者仍执着于单卡性能的比拼，却未察觉真正的算力革命早已发生在卡与卡之间的总线赛道上。
当 AI 大模型对卡间传输的需求以数月翻倍的速度狂飙，传统 PCIe 协议数年一代速率翻倍的迭代节奏早已捉襟见肘。
这场算力需求与传输技术的供需失衡直接引爆了全球 AI 行业的总线战争，谁能主导卡间互联的协议标准，谁就能掌握算力集群的生态话语权。
而这正是决定未来 AI 产业格局的核心战场。
英伟达对高端显卡的出口限制，本质上也是对高带宽互联技术的封锁。
这更印证了总线技术的战略重要性，单卡再强，若无法高效协同，也只是孤立的算力孤岛。
唯有打通卡间传输的高速公路，才能让万卡集群真正释放出颠覆式的算力。
一、为何总线战争是 AI 时代的必争之地？总线作为算力卡间数据流通的高速公路，其带宽、时延与兼容性直接决定了 AI 训练的效率上限。
在大模型参数规模突破万亿，算力集群规模达数千张卡的今天，总线的重要性被推向极致。
性能瓶颈的核心突破口：AI 训练中，卡间数据交换耗时占比已超计算本身。
传统 PCIE 5.0的传输速率远不能满足需求，而定制化互联协议能将时延压制到微秒级，带宽提升数倍。
成为突破算力天花板的关键。
生态霸权的前置战场：协议主导权意味着适配规则的制定权。
一旦某类协议形成规模效应，下游硬件厂商、软件开发者、数据中心都将被迫兼容，最终形成赢者通吃的生态壁垒。
自主可控的底层根基：总线控制器协议专利长期被欧美垄断。
若无法掌握自主协议，即便国产算力卡性能达标，也会因传输通道受制于人，陷入卡脖子困境。
二、当前总线战争的格局，四分天下。
面对 PCIe 的滞后性，全球科技巨头纷纷推出定制化互联协议，形成四大阵营割据的态势，各有核心优势与生态壁垒。
英伟达 NVLink 行业标杆级存在，凭借 H100、H200的市场垄断地位，实现卡间双向带宽超900GB 每秒，且与 CUDA 生态深度绑定。
其优势在于硬件加软件加协议的闭环。
缺点是封闭性极强，仅支持英伟达自家显卡，形成技术壁垒。
AMD Infinity Fabric 原 ULA Link ，主打异构兼容，可连接 CPU、GPU、FPGA 等多类设备，带宽与 NVLink 接近，且开放程度更高，试图依托服务器市场份额打破英伟达垄断。
但生态成熟度仍有差距。
谷歌 TPU interconnect 为自家 TPU 集群量身定制，聚焦云端大规模训练，具备超低时延的优势。
与 Google Cloud 的生态深度融合，但其应用场景高度集中，通用性不足。
华为 Matrix Link 国产阵营的核心力量，带宽达800GB 每秒以上，支持昇腾系列芯片的全互联。
且兼容 PCIe 协议，兼顾自主化与兼容性，是国内唯一能与国际巨头抗衡的协议方案，但生态覆盖范围仍需拓展。
此外，PCIe 联盟虽在推进6.0速率256GB每秒，7.0速率512GB每秒标准。
但按传统节奏，7.0全面商用需等到2030年前后，完全无法匹配 AI 算力的增长速度，已沦为备用选项。
三、国产阵营的现状：追赶加速，但痛点凸显。在国内算力自主化政策推动下，国产总线协议已实现从0到1的突破。
但仍处于追赶者地位，面临三大核心痛点，生态规模不足。
华为 Matrix Link 虽技术达标，但昇腾芯片的市场占有率仍低于英伟达，导致适配的软件框架、第三方硬件数量有限，形成技术可行，但生态不旺的困境。
专利与测试壁垒，欧美企业早于数十年布局总线专利，国产协议面临潜在侵权风险。
同时，协议测试设备认证体系被国外厂商垄断，制约了技术迭代与商业化落地。
协同性不足，国内除华为外，摩尔线程、壁仞等企业也在探索自有协议，缺乏统一的行业标准，导致资源分散。
难以形成合力对抗国际巨头。
但值得关注的是，国产阵营已呈现加速追赶态势，MatrixLink 已在政务、金融等国产化项目中规模化应用，曙光等厂商的算力机柜也已适配该协议，部分高校与科研机构开始共建协议测试平台，打破国外认证垄断。
四、国产突围的三大方向与未来趋势。
面对全球竞争，国产总线协议要实现突围，需聚焦技术迭代、生态共建、标准统一三大方向，同时顺应行业发展趋势。
一、技术上兼容加超越。
坚持自主化为主，兼容性为辅。
在提升协议带宽、降低时延的同时，保持对 PCIE 的兼容，降低数据中心迁移成本，快速扩大应用场景。
二、生态上开放加共建，联合国内硬件厂商、软件开发方、云服务商成立联盟。
开放协议接口，鼓励第三方适配，形成芯片协议软件应用的国产闭环，避免单打独斗。
三、标准上自主加参与，加快制定国产总线协议的行业标准，同时积极参与国际标准制定，争夺话语权，减少专利侵权风险。
二、未来发展趋势，协议专用化加融合化并行。
一方面，针对 AI 训练、边缘计算等场景的专用协议将持续迭代。
另一方面，兼容多场景的通用化协议将成为竞争焦点，兼顾效率与灵活性。
总线加光互联成为标配，为突破铜缆传输距离限制，光纤与定制化总线的结合将成为主流。
实现跨机柜、跨数据中心的高效互联，打破单机柜集群的规模上限。
国产协议规模化应用加国际化拓展，依托国内庞大的算力基建需求，国产协议将先实现规模化落地，再通过一带一路等合作契机，向海外拓展生态，打破欧美垄断。
总结，总线战争，关乎未来10年 AI 话语权。
这场总线战争，本质上是算力传输规则的争夺战，更是全球 AI 产业话语权的重新分配。
传统 PCIe 的滞后为后发者提供了弯道超车的机会，而国产阵营已站在关键的突围节点。
当前，国内虽面临生态、专利、标准等多重挑战，但凭借政策支持、庞大市场需求与技术突破，华为 Matrix Link 等方案已具备突围潜力。
未来，只有将技术自主与生态开放相结合，打破企业间的壁垒，形成国产协议的合力，才能在这场没有硝烟的战争中占据一席之地，为国产 AI 产业构建真正自主可控的底层传输根基。
而对于所有关注 AI 发展的人来说，是时候把目光从单卡性能上移开，卡间的总线赛道才是决定未来算力格局的终极战场。

英文翻译

The Bus War in the AI Era: A Domestic Breakthrough in the Struggle for Protocol Dominance

While everyone is still fixated on NVIDIA H200’s computing power and ASML’s lithography precision, the core battleground of AI large model training has quietly shifted.  
The improvement of single-card performance has approached the physical and cost limits, and the bandwidth and latency of inter-card data transmission are now the true bottlenecks constraining computational breakthroughs.  
Today’s AI training is no longer about single-card excellence but about the synergy of tens of thousands of cards.  
The efficiency of data flow between computing cards directly determines the speed and cost of large model training.  
Unfortunately, this critical pain point is not only overlooked by ordinary people but also by many industry practitioners who remain fixated on single-card performance comparisons, unaware that the real computing revolution has long taken place on the bus track between cards.  
As the demand for inter-card transmission in AI large models surges at a rate that doubles every few months, the iterative pace of traditional PCIe protocols—doubling speed every few years—has long fallen short.  
This imbalance between computing power demand and transmission technology has directly ignited a global bus war in the AI industry: whoever dominates the protocol standard for inter-card interconnection will control the ecological discourse power of computing clusters.  
And this is the core battlefield that will determine the future landscape of the AI industry.  
NVIDIA’s export restrictions on high-end graphics cards are, in essence, a blockade on high-bandwidth interconnect technology.  
This further underscores the strategic importance of bus technology: no matter how powerful a single card is, without efficient synergy, it remains an isolated island of computing power.  
Only by opening up the highway of inter-card transmission can a cluster of tens of thousands of cards truly unleash transformative computing power.

### 1. Why the Bus War is a Must-Fight Arena in the AI Era
As the highway for data flow between computing cards, a bus’s bandwidth, latency, and compatibility directly determine the upper limit of AI training efficiency.  
Today, with the parameter scale of large models exceeding trillions and computing clusters reaching thousands of cards, the importance of the bus has been pushed to the extreme.

**Core Breakthrough Point for Performance Bottlenecks:** In AI training, the time spent on inter-card data exchange has already exceeded that of computation itself.  
The transmission rate of traditional PCIe 5.0 is far from sufficient, while customized interconnect protocols can reduce latency to the microsecond level and increase bandwidth severalfold.  
This has become the key to breaking through the ceiling of computing power.

**Preliminary Battlefield for Ecological Hegemony:** Protocol dominance means the power to set adaptation rules.  
Once a certain protocol achieves scale, downstream hardware manufacturers, software developers, and data centers will be forced to comply, ultimately forming a winner-takes-all ecological barrier.

**Foundation for Self-Controlled Technology:** For a long time, bus controller protocol patents have been monopolized by Europe and the United States.  
Without mastering an independent protocol, even if domestic computing cards meet performance standards, they would still be constrained by transmission channels controlled by others, leading to a “bottleneck” dilemma.

### 2. The Current Landscape of the Bus War: Four Major Factions
Faced with PCIe’s lag, global tech giants have launched customized interconnect protocols, forming a situation of four major factions, each with core advantages and ecological barriers.

- **NVIDIA NVLink:** An industry benchmark. Leveraging the market monopoly of H100 and H200, it achieves inter-card bidirectional bandwidth exceeding 900 GB/s, deeply integrated with the CUDA ecosystem. Its advantage lies in a closed loop of hardware, software, and protocol. The drawback is extreme exclusivity—only supporting NVIDIA’s own GPUs, creating a technical barrier.

- **AMD Infinity Fabric (formerly ULA Link):** Focuses on heterogeneous compatibility, capable of connecting CPUs, GPUs, FPGAs, and other devices. Bandwidth is close to NVLink, and it is more open, attempting to break NVIDIA’s monopoly by leveraging server market share. However, its ecosystem maturity still lags.

- **Google TPU Interconnect:** Custom-built for Google’s TPU clusters, focusing on large-scale cloud training with ultra-low latency. It deeply integrates with Google Cloud’s ecosystem, but its application scenarios are highly concentrated, lacking generality.

- **Huawei Matrix Link:** The core force of the domestic camp. Bandwidth exceeds 800 GB/s, supporting full interconnection of the Ascend series chips. It is compatible with PCIe protocols, balancing autonomy and compatibility. It is the only domestic protocol that can compete with international giants, though its ecosystem coverage still needs expansion.

Additionally, the PCIe alliance is advancing the 6.0 (256 GB/s) and 7.0 (512 GB/s) standards.  
But following the traditional pace, full commercial use of 7.0 will not be until around 2030, completely unable to match the growth rate of AI computing power, relegating it to a backup option.

### 3. Current Status of the Domestic Camp: Catching Up but with Pain Points
Driven by domestic computing power autonomy policies, Chinese bus protocols have achieved a breakthrough from 0 to 1.  
However, they remain in a catch-up position, facing three major pain points:

- **Insufficient Ecosystem Scale:** Although Huawei’s Matrix Link meets technical standards, the market share of Ascend chips is still lower than NVIDIA’s, leading to limited adapted software frameworks and third-party hardware. This creates a dilemma of “technically feasible but ecologically weak.”

- **Patent and Testing Barriers:** European and American companies have laid out bus patents for decades, posing potential infringement risks for domestic protocols. Meanwhile, the protocol testing equipment and certification system are monopolized by foreign manufacturers, constraining technological iteration and commercial deployment.

- **Lack of Synergy:** Apart from Huawei, domestic companies like Moore Threads and Biren are also exploring their own protocols, lacking unified industry standards, which leads to resource dispersion and difficulty in forming a collective force against international giants.

However, it is worth noting that the domestic camp is showing an accelerated catch-up trend. Matrix Link has been deployed on a large scale in government and financial projects that require domestic solutions. Manufacturers like Dawning have also adapted their computing cabinets to this protocol. Some universities and research institutions are beginning to co-build protocol testing platforms, breaking foreign certification monopolies.

### 4. Three Major Directions and Future Trends for Domestic Breakthrough
To achieve a breakthrough in the face of global competition, domestic bus protocols must focus on three directions: technological iteration, ecosystem co-building, and standard unification, while keeping pace with industry trends.

**1. Technology: Compatibility + Surpassing**  
Adhere to autonomy as the primary goal, with compatibility as a supplement. While improving protocol bandwidth and reducing latency, maintain compatibility with PCIe to lower the cost of data center migration and rapidly expand application scenarios.

**2. Ecosystem: Openness + Co-building**  
Form an alliance with domestic hardware manufacturers, software developers, and cloud service providers. Open protocol interfaces and encourage third-party adaptation to create a closed-loop domestic ecosystem of chips, protocols, software, and applications, avoiding isolated efforts.

**3. Standards: Autonomy + Participation**  
Accelerate the formulation of industry standards for domestic bus protocols while actively participating in international standard setting to gain a voice and reduce patent infringement risks.

**Future Development Trends:**  
- **Protocol specialization + convergence:** On one hand, dedicated protocols for scenarios like AI training and edge computing will continue to iterate. On the other hand, general-purpose protocols that are compatible with multiple scenarios will become a competitive focus, balancing efficiency and flexibility.  
- **Bus + optical interconnection becomes mainstream:** To overcome the distance limitations of copper cables, the combination of optical fiber and customized buses will become the norm, enabling efficient cross-cabinet and cross-data-center interconnection, breaking the scale limit of single-cabinet clusters.  
- **Large-scale application of domestic protocols + international expansion:** Leveraging domestic demand for computing power infrastructure, domestic protocols will first achieve large-scale deployment, then expand overseas through cooperation opportunities like the Belt and Road Initiative, breaking the European-American monopoly.

### Conclusion: The Bus War Concerns the Next Decade of AI Discourse Power
This bus war is essentially a battle over the rules of computing power transmission and a redistribution of global AI industry discourse.  
The lag of traditional PCIe provides a late-mover advantage for overtaking on curves, and the domestic camp now stands at a critical breakthrough point.  
Currently, despite multiple challenges such as ecosystem, patents, and standards, with policy support, huge market demand, and technological breakthroughs, solutions like Huawei’s Matrix Link already have the potential to break through.  
In the future, only by combining technological autonomy with ecosystem openness, breaking down barriers between enterprises, and forming a unified force of domestic protocols can we secure a place in this silent war and build a truly self-controllable underlying transmission foundation for the domestic AI industry.  
For everyone concerned about AI development, it is time to shift focus from single-card performance—the bus track between cards is the ultimate battleground that will determine the future landscape of computing power.